1. Field of the Invention
The present invention relates to a circuit for processing vertical synchronization signals including a circuit for detecting the polarity of the received signals.
2. Discussion of the Related Art
To control the display of images on a cathode-ray tube of a monitor or of a television screen and, more specifically, to control the scanning of an electron beam on a screen, synchronization signals are used. The synchronization signals contain time information enabling determination of the beginning of the lines (horizontal synchronization) and of the frames (vertical synchronization). A frame is the set of lines required to form an image on a screen. The synchronization signals are logic pulse signals mainly defined by the polarity of their pulses (which is positive or negative according to whether the rising edges or the falling edges are taken into account), the recurrence frequency of the pulses, and their duration.
The vertical synchronization signals are transmitted directly, or in a compound signal including both the vertical and horizontal synchronization signals.
A conventional method for controlling the vertical scanning consists in generating, by means of an oscillator, a sawtooth-shaped signal based on the received vertical synchronization pulse signal. If the received signal is a compound signal, a vertical synchronization signal extracted from the compound signal will have been previously provided, this extracted signal being then used to generate the sawtooth-shaped signal. The sawtooth-shaped signal conventionally has the same frequency as the received pulse signal and a fixed amplitude (this latter characteristic being controlled by an automatic gain control loop, or AGC).
FIG. 1 schematically illustrates a circuit 2 for processing a vertical synchronization signal VIN. Circuits TDA 9103 and TDA 9105 of SGS-THOMSON Microelectronics implement such a circuit. Circuit 2 includes an input 4 for receiving signal VIN which can be of positive or negative polarity. The vertical display is always constructed in the same way (from the top of the screen to the bottom), an input interface circuit 6 receives signal VIN and generates from this signal a logic pulse signal SYNC of fixed polarity and having a recurrence frequency identical to that of signal VIN. It will be for example assumed that signal SYNC has a negative polarity. This signal SYNC is supplied to an oscillator control circuit 8. This circuit 8 controls the charge and the discharge of a capacitor 10 across which a sawtooth-shaped signal VOSC is generated. Capacitor 10 is charged with a current IOSC supplied by an automatic gain control loop 12.
A switch (in FIG. 1, it is a MOS-type N-channel transistor 14) and a resistor 16, mounted in series, are placed in parallel across capacitor 10. The switch is controlled by circuit 8 so that the capacitor charges when the switch is open, and that it discharges through the switch when the switch is closed.
Signal VOSC is supplied to circuit 8 via an operational amplifier 18 mounted as a follower (the signal supplied by amplifier 18 is referred to as VOUT). Circuit 8 includes a comparator circuit for comparing signal VOUT with a potential VMIN, and an edge detector, so that the sawtooth-shaped signal oscillates between value VMIN and a value corresponding to the occurrence of a type of edge in signal SYNC, for example, the falling edges. Thus, signal VOSC has a frequency corresponding to the frequency of the received synchronization signal. To ensure that signal VOSC has a constant amplitude, the automatic gain control circuit which controls the charge current of capacitor 10 is used, so that the value reached by signal VOSC upon occurrence of the falling edges in signal SYNC corresponds to a check value.
Finally, signal VOUT is supplied to an output stage 20 which will issue a sawtooth-shaped signal CDV. The output stage will, for example, set the gain and the mean value of output signal CDV. The sawtooth-shaped signal CDV is supplied to a circuit which converts it into a current signal, this current signal being issued to the vertical deflectors.
FIG. 2 illustrates an example of implementation of an input interface circuit 6. It is assumed that an output signal SYNC with a negative polarity is provided, whatever the polarity of the signal VIN received. It will further be assumed that signal VIN is at a potential VCC of 5 volts when it is in the high state and at a ground potential GND of 0 volts when it is in the low state, and that signal SYNC is at a potential VH of 8 volts when it is in the high state and at potential GND when it is in the low state. The logic circuits of circuit 6 will be supplied by potentials VCC, VH, and GND.
Circuit 6 includes an input comparator 22 which receives signal VIN on its "-" input and a potential REF1, for example from 2 to 2.5 volts, on its "+" input. This comparator provides a logic signal A. An inverter 24 receives signal A as an input and provides a logic signal B, which is the inverse of signal A.
Signal A controls a switch 26 mounted between the ground and the input of an inverter 28. The switch is open when signal A is in a first state, and it is closed when signal A is in a second state. In the example described, the first state will be the low state and the second state is the high state. A current source 30 providing a current 211 and, on the other hand, a capacitor 32, are mounted in parallel to switch 26. A current source 34 is connected to the input of inverter 28. It provides a current I1. Thus, capacitor 32 will be charged or discharged with a constant current, according to whether switch 26 is closed or open. The potential at the input of inverter 28 will be referred to as VC1.
Inverter 28 provides a logic signal D. This signal D is inverted in an inverter 36 and the logic signal generated by inverter 36 is referred to as E. This signal E and signal B are supplied to a two-input NOR-type logic gate 38 which provides a logic signal SET1. Besides, signals D and A are supplied to a two-input NOR-type gate 40 which provides a logic signal SET2.
An RS-type double flip-flop 42 receives signals SET1 and SET2 on its set inputs (referred to as S1 and S2). The flip-flop further receives logic control signals RESET and SECINH on its reset inputs (referred to as R1 and R2). Signal SECINH is, for example, provided by a starting detection circuit so that it switches from a first to a second state when the circuit is supplied. It is here assumed that the first and second states respectively are the low state and the high state. Signal RESET sets the duration of the pulses in signal SYNC. It is typically generated based on the detection of two thresholds on the sawtooth-shaped signal generated by capacitor 10. Flip-flop 42 provides a logic signal F. Signal F is inverted in an inverter 44 which provides a logic signal NF, which is the inverse of signal F. Signal NF is used to control a switch 46 mounted between the ground and a first terminal of a capacitor 48. The second terminal of capacitor 48 is connected to the ground. A current source 50 provides a current I2. It is connected to the first terminal of capacitor 48, so that capacitor 48 is charged or discharged with a constant current according to whether switch 46 is open or closed. The voltage across capacitor 48 will be referred to as VC2. Voltage VC2 is compared to a fixed potential REF2, for example from 6 to 7 volts, in a comparator 52. This comparator provides a logic signal G which is representative of the result of the comparison. This signal is inverted in an inverter 54, which provides a logic signal NG. An inverter 56 inverts signal NG to provide logic signal SYNC. Signals SYNC and F are supplied to a two-input NAND-type logic gate 58 which provides a logic signal NSAMP. This signal is inverted in an inverter 60 which provides a logic signal SAMP which is the inverse of signal NSAMP.
Assume, as illustrated in FIGS. 5a to 5e showing signals VIN, SAMP, SYNC, VOSC, and RESET, that signal VIN is of positive polarity. The synchronization pulses are characterized by a rising edge subsequently followed by a falling edge. Further assume that signals SAMP, B, D, SET1, SET2, F, and VC2 are in the low state, and that signals SYNC, A, VC1, and G are in the high state.
When the rising edge marking the beginning of the pulse appears, signal A switches to the low state when the switching threshold of comparator 22 is reached. Switch 26 is then open and capacitor 32 discharges with a constant current. Concurrently, signal SET1 switches to the high state. It remains in this high state as long as the switching threshold of inverter 28, which could be placed at 4 volts, is not reached and signal E has not changed state. Signal F will thus switch to the high state. Accordingly, capacitor 48 starts charging. Concurrently, signal NSAMP switches to the low state, and signal SAMP switches to the high state. Once threshold REF2 has been reached by signal VC2, signal G (and accordingly, signal SYNC) switches to the low state. This induces signal SAMP to switch back to its original state. Potential REF2 will set the delay during which signal SAMP is in the high state.
When the rising edge marking the end of the synchronization pulse appears, signal A switches back to the high state. Capacitor 32 will thus be charged again. As long as the switching threshold of inverter 28 is not reached, both signals B and E are in the low state. Signal SET2 will thus rise to the high state during this time interval. Once the threshold has been reached, signal E switches to the high state and signal SET2 switches back to the low state. To mark the end of the negative pulse in SYNC, it is enough to provide a rising edge in signal RESET. The signals are then set back to their initial states.
If it is assumed that signal VIN is negatively polarized, a signal SYNC with a negative polarity will be similarly provided. Conversely, the setting signal SYNC to the low state will be controlled by signal SET2 which will mark the beginning of the synchronization pulses.
FIG. 3 illustrates an example of implementation of circuit 12.
It includes an input 62 for receiving the signal VOSC to be regulated, an input 64 for receiving a check signal VREF, an input 66 for receiving signal SAMP, an input 68 for receiving a logic enable control signal NOSYNCHRO and an output 70 for providing the output current IOSC.
Input 62 is connected to an amplifier 72 mounted as a follower which provides a signal VOSCA. The "+" input of amplifier 72 is connected to input 62. Its "-" input is connected to its output. Amplifier 72 allows the input impedance of circuit 12 to be controlled so that no current is taken from capacitor 10. The output of amplifier 72 is connected to the "+" input of an amplifier 74. The "-" input of this amplifier 74 is connected on the one hand to input 64 via a resistor 76 and on the other hand to its output, via a resistor 78. The output of amplifier 74 is also connected to a first pole of a capacitor 84, via a resistor 80 and a switch 82 mounted in series. Switch 82 is controlled by signal SAMP. The switch will be implemented so as to be closed if signal SAMP is in the high state, and open otherwise. The second pole of capacitor 84 is connected to a ground. The voltage across capacitor 84 is referred to as VSAMP. The first pole of this capacitor is further connected to input 64 via a switch 86 controlled by signal NOSYNCHRO and to the "+" input of an amplifier 88 mounted as a follower. The "-" input of amplifier 88 is connected to its output. Input 64 is connected to the "+" input of an amplifier 92 mounted as a follower. The "-" input of this amplifier is connected to its output. The outputs of amplifiers 92 and 88 are interconnected via a resistor 90. A current mirror 94 copies the current I'0 running through this resistor. A current source 96 further provides a reference current I0. Current mirror 94 and current source 96 are connected to output 70, so that this output provides current IOSC by adding currents I0 and I'0.
Let Cosc be the value of capacitor 10. Cosc.VOSC=IOSC.T with T corresponding to the charging time of capacitor 10, assuming a very fast discharge. 10 is constant and I'0=(VREF-VSAMP)/R with R being the value of resistor 90. If the potential provided at the output of amplifier 74 is referred to as V1, the potential on the "-" input of this amplifier is referred to as Vh and the values of resistors 78 and 76 are referred to as R1 and R2, then (V1-Vh)/R2=(Vh-VREF)/R2.
Thus, V1=A.(Vh-VREF)+VREF with A=1=R1/R2.
When switch 82 closes, then capacitor 84 charges until VSAMP=V1. Signal VOSC is then close to its maximum value before the discharge on the falling edge of signal SYNC. Then, I'O=A.(VREF-Vh)/R. The system converges towards Vh=VREF, which then practically corresponds to the maximum value reached by signal VOSC, with this signal VOSC then oscillating between VMIN and VREF at a frequency f=1/T which is the recurrence frequency of the received vertical synchronization pulses. Signal NOSYNCHRO allows the potential VREF to be applied to the input of amplifier 88, typically in the absence of a synchronization signal to be processed. Then, IOSC=I0. Circuit 2 then provides a signal VOSC with a so-called free frequency, the value of which is given by the value of current I0.
An aim of the present invention is to provide a vertical synchronization processing circuit such as illustrated in FIGS. 1 and 2, which includes a circuit for detecting the polarity of the received synchronization signal.
A solution is to provide an analog detection. This solution is difficult to implement. As an example, in monitors, the recurrence frequency may range from 50 to 165 hertz, which corresponds to a period which can range from 6 to 20 milliseconds. According to screen display standards, the width of the synchronization pulses may reach 15% of the period, that is, up to 3 milliseconds. To detect the polarity of such pulses, a time constant of 3 milliseconds at least may be implemented, which would require a large capacitance (several tens of picofarads) which is not easily integrable, and a current of low value (several tens of nanoamperes) which is not easily implementable.